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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 20511 rev: c amendment/ +1 issue date: may 1997 3.0 v-only flash AM29LV008T/am29lv008b 8 megabit (1,048,576 x 8-bit) cmos 3.0 volt-only, sectored flash memory distinctive characteristics n single power supply operation extended voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications standard voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors n high performance extended voltage range: access times as fast as 100 ns standard voltage range: access times as fast as 90 ns n ultra low power consumption automatic sleep mode: 200 na typical standby mode: 200 na typical read mode: 2 ma/mhz typical program/erase mode: 20 ma typical n flexible sector architecture one 16 kbyte, two 8 kbyte, one 32 kbyte, and ?teen 64 kbyte sectors supports control code and data storage on a single device sector protection features: a hardware method of locking a sector to prevent any program or erase operations within that sector temporary sector unprotect feature allows code changes in previously locked sectors n top or bottom boot block con?urations available n embedded algorithms embedded erase algorithms automatically preprogram and erase the entire chip or any combination of designated sectors embedded program algorithms automatically write and verify bytes or words at speci?d addresses n minimum 100,000 write cycle guarantee per sector n package option 40-pin tsop n compatibility with jedec standards pinout and software compatible with single- power supply flash superior inadvertent write protection n data polling and toggle bits provides a software method of detecting program or erase operation completion n ready/busy pin provides a hardware method of detecting program or erase cycle completion n erase suspend/resume feature provides the ability to suspend the erase operation in any sector, read data from or program data to any other sector, then return to the original sector and complete the initial erase operation n hardware reset pin (reset ) hardware method to reset the device to the read mode general description the am29lv008 is an 8 mbit, 3.0 volt-only flash mem- ory organized as 512 kbytes of 8 bits each. for ?xible erase and program capability, the 512 kbits of data is divided into 19 sectors of one 16 kbyte, two 8 kbyte, one 32 kbyte, and ?teen 64 kbytes. the data appears on dq0?q7. the am29lv008 is offered in a 40-pin tsop package. this device is designed to be pro- grammed in-system with the standard system 3.0 volt v cc supply. the device can also be reprogrammed in standard eprom programmers. the am29lv008 provides two levels of performance. the ?st level offers access times as fast as 100 ns with a v cc range as low as 2.7 volts, which is optimal for battery powered applications. the second level offers a
2 AM29LV008T/am29lv008b preliminary 90 ns access time, optimizing performance in systems where the power supply is in the regulated range of 3.0 to 3.6 volts. to eliminate bus contention, the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the am29lv008 is entirely command set-compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. write cy- cles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. the am29lv008 is programmed by executing the pro- gram command sequence. this invokes the embedded program algorithm, which is an internal algorithm that automatically times the program pulse widths and veri- ?s proper cell margin. the device is erased by execut- ing the erase command sequence. this invokes the embedded erase algorithm, which is an internal algo- rithm that automatically preprograms the array, if it is not already programmed, before executing the erase operation. during erase, the device automatically times the erase pulse widths and veri?s proper cell margin. this device also features a sector erase architecture. this allows for sectors of memory to be erased and re- programmed without affecting the data contents of other sectors. a sector is typically erased and veri?d within 1.0 second. the am29lv008 is fully erased when shipped from the factory. the am29lv008 device also features hardware sector protection, implemented via external programming equipment, which disables both program and erase op- erations in any combination of the memory sectors. the erase suspend feature enables the user to pause the erase operation, for any period of time, to read data from or program data to a sector that was not being erased. thus, true background erase can be achieved. the device features 3.0 volt, single-power-supply oper- ation for both read and write functions. internally gen- erated and regulated voltages are provided for the program and erase operations. a low v cc detector au- tomatically inhibits write operations during power tran- sitions. the end of program or erase is detected by the ry/by pin. data polling of dq7, or by the toggle bit (dq6). once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. the am29lv008 also has a hardware reset pin. when this pin is driven low, execution of any embed- ded program or erase algorithm will be terminated. the internal state machine is then be reset into the read mode. resetting the device will enable the sys- tems microprocessor to read the boot-up ?mware from the flash memory. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the am29lv008 memory electrically erases all bits within a sector simultaneously via fowler- nordheim tunneling. the bytes are programmed one byte at a time using the eprom programming mecha- nism of hot electron injection.
AM29LV008T/am29lv008b 3 preliminary 3.0 v-only flash product selector guide block diagram family part number AM29LV008T/am29lv008b ordering part number: v cc = 3.0?.6 v -90r v cc = 2.7?.6 v -100 -120 -150 max access time (ns) 90 100 120 150 ce access time (ns) 90 100 120 150 oe access time (ns) 40 40 50 55 20511c-1 erase voltage generator input/output buffers data latch y-gating cell matrix x-decoder y-decoder chip enable output enable logic pgm voltage generator timer v cc detector state control command register we ce oe a0?19 stb stb dq0?q7 ry/by byte reset v cc v ss sector switches address latch
4 AM29LV008T/am29lv008b preliminary connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we reset nc ry/by a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss nc a19 a10 dq7 dq6 dq5 ce v ss ce a0 dq4 v cc v cc nc dq3 dq2 dq1 20511c-2 reverse 40-pin tsop standard 40-pin tsop 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we reset nc ry/by a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss nc a19 a10 dq7 dq6 dq5 oe v ss ce a0 dq4 v cc v cc nc dq3 dq2 dq1
AM29LV008T/am29lv008b 5 preliminary 3.0 v-only flash pin configuration a0?19 = 20 addresses dq0?q7 = 8 data inputs/outputs ce = chip enable oe = output enable we = write enable reset = hardware reset pin, active low ry/by = ready/busy output v cc = standard voltage range (3.0 v to 3.6 v) for -90r extended voltage range (2.7 to 3.6 v) for -100, -120, -150 v ss = device ground nc = pin not connected internally logic symbol 20 8 dq0?q7 a0?19 ce (e ) oe (g ) we (w ) 20511c-3 reset ry/by
6 AM29LV008T/am29lv008b preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. device number/description am29lv008 8 megabit (1 m x 8-bit) cmos flash memory 3.0 volt-only program and erase optional processing blank = standard processing b = burn-in temperature range c = commercial (0 c to +70 c) i = industrial (?0 c to +85 c) e = extended (?5 c to +125 c) package type e = 40-pin thin small outline package (tsop) standard pinout (ts 040) f = 40-pin thin small outline package (tsop) reverse pinout (tsr040) speed option -xxx = 2.7 to 3.6 v v cc -xxr = 3.0 to 3.6 v v cc see product selector guide and valid combinations c e -90r am29lv008 t boot code sector architecture t = top sector b = bottom sector valid combinations AM29LV008T-90r, am29lv008b-90r v cc = 3.0?.6 v ec, ei, fc, fi AM29LV008T-100, am29lv008b-100 ec, ei, ee, eeb, fc, fi, fe, feb AM29LV008T-120, am29lv008b-120 AM29LV008T-150, am29lv008b-150
AM29LV008T/am29lv008b 7 preliminary 3.0 v-only flash table 1. am29lv008 user bus operations legend: l = v il , h = v ih , v id = 12.0 v 5%, x = don? care. see ?c characteristics on page 26 for voltage levels. pd = program data, rd = read data. refer to table 3 on page 10 for more information. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 5 on page 13. 2. refer to table 5 for valid pd during a write operation. 3. set v cc = 3.0 volts 10%. 4. refer to ?ector protection on page 12. operation ce oe we a0 a1 a6 a9 dq0?q7 reset autoselect, manufacturer code (note 1) ll h lllv id code h autoselect, device code (note 1) l l h h l l v id code h read l l h a0 a1 a6 a9 rd h standby h x x xxxx high z h output disable l h h xxxx high z h write l h l a0 a1 a6 a9 pd (note 2) h enable sector protect (note 3) l v id pulse/h l h l v id code h verify sector protect (note 4) l l h l h l v id code h temporary sector unprotect x x x xxxx x v id reset x x x xxxx high z l
8 AM29LV008T/am29lv008b preliminary user bus operations read mode the am29lv008 has three control functions which must be satis?d in order to obtain data at the outputs: n ce is the power control and should be used for de- vice selection (ce = v il ) n oe is the output control and should be used to gate data to the output pins if the device is selected (oe = v il ) n we remains at v ih address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the out- put enable access time (t oe ) is the delay from the fall- ing edge of oe to valid data at the output pins (assuming the addresses have been stable at least t acc ?t oe time). standby mode the am29lv008 is designed to accommodate low standby power consumption by applying the following voltages to the ce and reset pins: i cc3 for cmos compatible i/os (current consumption <5 m a max.) is enabled when a cmos logic level ? (v cc 0.3 v) is applied to the ce control pin with reset = v cc 0.3 v. while in the i cc3 standby mode, the data i/o pins re- main in the high impedance state independent of the voltage level applied to the oe input. see the dc char- acteristics section for more details on standby modes. deselecting ce (ce and reset = v cc 0.3 v) puts the device into the i cc3 standby mode. if the device is deselected during an embedded algorithm operation, it continues to draw active power (i cc2 ) prior to entering the standby mode, until the operation is complete. when the device is again selected (ce = v il ), active operations occur in accordance with the ac timing speci?ations. automatic sleep mode advanced power management features such as the automatic sleep mode minimize flash device energy consumption. this is extremely important in battery-powered applications. the am29lv008 auto- matically enables the low-power, automatic sleep mode when addresses remain stable for 200 ns. auto- matic sleep mode is independent of the ce , we , and oe control signals. typical sleep mode current draw is 200 na (for cmos-compatible operation). standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. output disable if the oe input is at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state.
AM29LV008T/am29lv008b 9 preliminary 3.0 v-only flash autoselect the autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. the intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the au- toselect command may also be used to check the sta- tus of write-protected sectors (see table 2). this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (12.0 v 5%) on address pin a9. two identi?r bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all ad- dresses are don? cares except a0, a1, and a6 see table 2. the manufacturer and device codes may also be read via the command register, for instances when the am29lv008 is erased or programmed in a system with- out access to high voltage on the a9 pin. the command sequence is illustrated in table 5 on page 13. byte 0 (a0 = v il ) represents the manufacturers code and byte 1 (a0 = v ih ) the device identi?r code. for the am29lv008 these two bytes are given in table 2. all identi?rs for manufacturer and device will exhibit odd parity with dq7 de?ed as the parity bit. in order to read the proper device codes when executing autose- lect, a1 must be v il (see table 2). the device code is 3eh (for top boot block) or 37h (for bottom boot block). in order to determine which sectors are write protected, a1 must be at v ih while running through the sector ad- dresses; if the selected sector is protected, a logical ? will be output on dq0 (dq0 = 1). table 2. autoselect/sector protection codes x = don? care. * outputs 01h at protected sector addresses. type a13?19 a6 a1 a0 code (hex) dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer code: amd x l l l 01h 00000001 29lv008 device (top boot block) x llh 3eh 00111110 29lv008 device (bottom boot block) x llh 37h 00110111 sector protection set sector addresses l h l 01h* 00000001
10 AM29LV008T/am29lv008b preliminary table 3. sector address tables (AM29LV008T) a19 a18 a17 a16 a15 a14 a13 sector size address range sa00000xxx 64 kb ytes 00000h-0ffffh sa10001xxx 64 kb ytes 10000h-1ffffh sa20010xxx 64 kb ytes 20000h-2ffffh sa30011xxx 64 kb ytes 30000h-3ffffh sa40100xxx 64 kb ytes 40000h-4ffffh sa50101xxx 64 kb ytes 50000h-5ffffh sa60110xxx 64 kb ytes 60000h-6ffffh sa70111xxx 64 kb ytes 70000h-7ffffh sa81000xxx 64 kb ytes 80000h-8ffffh sa91001xxx 64 kb ytes 90000h-9ffffh sa10 1010xxx 64 kb ytes a0000h-affffh sa11 1011xxx 64 kb ytes b0000h-bffffh sa12 1100xxx 64 kb ytes c0000h-cffffh sa13 1101xxx 64 kb ytes d0000h-dffffh sa14 1110xxx 64 kb ytes e0000h-effffh sa15 11110xx 32 kb ytes f0000h-f7fffh sa16 1111100 8 kb ytes f8000h-f9fffh sa17 1111101 8 kb ytes fa000h-fbfffh sa18 111111x 16 kb ytes fc000h-fffffh
AM29LV008T/am29lv008b 11 preliminary 3.0 v-only flash table 4. sector address tables (am29lv008b) a19 a18 a17 a16 a15 a14 a13 sector size address range sa0000000x 16 kb ytes 00000h-03fffh sa10000010 8 kb ytes 04000h-05fffh sa20000011 8 kb ytes 06000h-07fffh sa300001xx 32 kb ytes 08000h-0ffffh sa40001xxx 64 kb ytes 10000h-1ffffh sa50010xxx 64 kb ytes 20000h-2ffffh sa60011xxx 64 kb ytes 30000h-3ffffh sa70100xxx 64 kb ytes 40000h-4ffffh sa80101xxx 64 kb ytes 50000h-5ffffh sa90110xxx 64 kb ytes 60000h-6ffffh sa10 0111xxx 64 kb ytes 70000h-7ffffh sa11 1000xxx 64 kb ytes 80000h-8ffffh sa12 1001xxx 64 kb ytes 90000h-9ffffh sa13 1010xxx 64 kb ytes a0000h-affffh sa14 1011xxx 64 kb ytes b0000h-bffffh sa15 1100xxx 64 kb ytes c0000h-cffffh sa16 1101xxx 64 kb ytes d0000h-dffffh sa17 1110xxx 64 kb ytes e0000h-effffh sa18 1111xxx 64 kb ytes f0000h-fffffh
12 AM29LV008T/am29lv008b preliminary write device erasure and programming are accomplished via the command register. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of ce or we , whichever occurs later, while data is latched on the rising edge of the ce or we pulse, whichever occurs ?st. standard microprocessor write timings are used. refer to ac write characteristics and the erase/ programming waveforms for speci? timing parameters. sector protection sectors of the am29lv008 may be hardware protected at the users factory with external programming equip- ment. the protection circuitry will disable both program and erase functions for the protected sectors, making the protected sectors read-only. requests to program or erase a protected sector will be ignored by the de- vice. if the user attempts to write to a protected sector, d a t a polling will be activated for about 1 m s; the device will then return to read mode, with data from the pro- tected sector unchanged. if the user attempts to erase a protected sector, toggle bit will be activated for about 50 m s; the device will then return to read mode, without having erased the protected sector. it is possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order address a18?12 represents the sec- tor address, will produce a logical ? at dq0 for a pro- tected sector. temporary sector unprotect the sectors of the am29lv008 may be temporarily un- protected by raising the reset pin to 12.0 volts (v id ). during this mode, formerly protected sectors can be programmed or erased with standard command se- quences by selecting the appropriate byte or sector ad- dresses. once the reset pin goes to v ih , all the previously protected sectors will be protected again. command de?itions device operations are selected by writing speci? ad- dress and data sequences into the command register. writing incorrect address and data values or writ- ing them in the improper sequence will reset the device to the read mode. table 5 on page 13 de?es the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) com- mands are valid only while the sector erase operation is in progress. read/reset command the device will automatically power up in the read/ reset state. in this case, a command sequence is not required to read data. standard microproces- sor cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transi- tion. refer to the ac characteristics section for the speci? timing parameters. the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer and device codes must be accessible while the device resides in the target system. the am29lv008 contains an autoselect command opera- tion that provides device information and sector protec- tion status to the system. the operation is initiated by writing the autoselect command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufac- turer code of 01h. a read cycle from address xx01h returns the device code 3eh (for top boot device) or 37h (for bottom boot device); see table 2 on page 9. all manufacturer and device codes will exhibit odd par- ity with the msb of the lower byte (dq7) de?ed as the parity bit. scanning the sector addresses (a13, a14, a15, a16, a17, a18, and a19) while (a6, a1, a0) = (0, 1, 0) will produce a logical ? code at device output dq0 for a write protected sector (see table 2). to terminate the autoselect operation, it is neces- sary to write the read/reset command sequence into the register.
AM29LV008T/am29lv008b 13 preliminary 3.0 v-only flash table 5. am29lv008 command de?itions legend: ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we or ce pulse. pd = data to be programmed at location pa. data is latched on the rising edge of we or ce pulse. sa = address of the sector to be erased or veri?d. address bits a19?13 uniquely select any sector. notes: 1. all values are in hexadecimal. 2. see table 1 for description of bus operations. 3. the data is 00h for an unprotected sector and 01h for a protected sector. the complete bus address is composed of the sector address on a19?13 and 02h on a7?0. 4. read and program functions in non-erasing sectors are allowed in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 5. the erase resume command is valid only during the erase suspend mode. 6. unless otherwise noted, address bits a19?11 = x = don? care. byte programming the device is programmed on a byte-by-byte basis. programming is a four-bus-cycle operation. there are two ?nlock write cycles. these are followed by the program command and address/data write cy- cles. addresses are latched on the falling edge of ce or we , whichever occurs later, while the data is latched on the rising edge of ce or we , whichever occurs ?st. the rising edge of ce or we , whichever occurs rst, initiates programming using the em- bedded program algorithm. upon executing the write command, the system is not required to pro- vide further controls or timing. the device will auto- matically provide adequate internally generated program pulses and verify the programmed cell margin. the status of the embedded program algorithm op- eration can be determined three ways: n d a t a polling of dq7 command sequence read/reset (note 2) bus write cycles reqd first bus write cycle second bus read/write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data reset/read 1 xxx f0 ra rd autoselect manufacturer id 3 555 aa 2aa 55 555 90 x00 01 autoselect device id (top boot block) 3 555 aa 2aa 55 555 90 x01 3e autoselect device id (bottom boot block) 3 555 aa 2aa 55 555 90 x01 37 autoselect sector protect verify (note 3) 3 555 aa 2aa 55 555 90 sa x02 00 01 byte program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 4) 1 xxx b0 erase resume (note 5) 1 xxx 30
14 AM29LV008T/am29lv008b preliminary n checking the status of the toggle bit dq6 n checking the status of the ry/by pin any commands written to the chip during the em- bedded program algorithm will be ignored. if a hardware reset occurs during a programming oper- ation, the data at that location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data ? cannot be programmed back to a ?? attempting to do so will cause the device to exceed programming time limits (dq5 = 1) or result in an apparent suc- cess according to the data polling algorithm. how- ever, reading the device after executing the read/ reset operation will show that the data is still ?? only erase operations can convert ?s to ?s. figure 4 illustrates the embedded program algorithm, using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two ?nlock write cycles, followed by writing the erase ?et up command. two more ?nlock write cycles are fol- lowed by the chip erase command. chip erase does not require the user to preprogram the device to all ?s prior to erase. upon executing the em- bedded erase algorithm command sequence, the de- vice automatically programs and veri?s the entire memory to an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. the embedded erase algorithm erase begins on the rising edge of the last we or ce (whichever occurs ?st) pulse in the command sequence. the status of the embedded erase algorithm operation can be deter- mined three ways: n d a t a polling of dq7 n checking the status of the toggle bit dq6 n checking the status of the ry/by pin figure 5 illustrates the embedded erase algorithm, using a typical command sequence and bus opera- tions. sector erase sector erase is a six bus cycle operation. there are two ?nlock writes. these are followed by writing the erase ?et up command. two more ?nlock writes are fol- lowed by the sector erase command (30h). the sector address (any address location within the desired sec- tor) is latched on the falling edge of we or ce (which- ever occurs last) while the command (30h) is latched on the rising edge of we or ce (whichever occurs ?st). multiple sectors can be specied for erase by writing the six bus cycle operation as described above and then following it by additional writes of the sector erase command to addresses of other sectors to be erased. the time between sector erase command writes must be less than 80 m s, otherwise that command will not be accepted. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 80 m s from the rising edge of the last we (or ce ) will initiate the exe- cution of the sector erase command(s). if another fall- ing edge of the we (or ce ) occurs within the 80 m s time-out window, the timer is reset. during the 80 m s window, any command other than sector erase or erase suspend written to the device will reset the de- vice back to read mode. once the 80 m s window has timed out, only the erase suspend command is recog- nized. note that although the reset command is not recognized in the erase suspend mode, the device is available for read or program operations in sectors that are not erase suspended. the erase suspended and erase resume commands may be written as often as required during a sector erase operation. hence, once erase has begun, it must ultimately complete unless hardware reset is initiated. loading the sector erase registers may be done in any sequence and with any number of sectors (0 to 18). sector erase does not require the user to program the device prior to erase. the device automatically prepro- grams all memory locations, within sectors to be erased, prior to electrical erase. when erasing a sector or sectors, the remaining unselected sectors or the write protected sectors are unaffected. the system is not required to provide any controls or timings during sector erase operations. the erase suspend and erase resume commands may be written as often as required during a sector erase operation. automatic sector erase operations begin on the rising edge of the we (or ce ) pulse of the last sector erase command issued, and once the 80 m s time-out window has expired. the status of the sector erase operation can be determined three ways: n d a t a polling of dq7 n checking the status of the toggle bit dq6 n checking the status of the ry/by pin further status of device activity during the sector erase operation can be determined using toggle bits dq2 and dq3. figure 5 illustrates the embedded erase algorithm, using a typical command sequence and bus opera- tions. erase suspend the erase suspend command allows the user to inter- rupt a sector erase operation and then perform data
AM29LV008T/am29lv008b 15 preliminary 3.0 v-only flash read or programs in a sector not being erased. this command is applicable only during the sector erase operation, which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the execution of the chip erase opera- tion or embedded program algorithm (but will reset the chip if written improperly during the command se- quences.) writing the erase suspend command during the sector erase time-out results in immediate termina- tion of the time-out period and suspension of the erase operation. once in erase suspend, the device is avail- able for read (note that in the erase suspend mode, the reset/read command is not required for read opera- tions and is ignored) or program operations in sectors not being erased. any other command written during the erase suspend mode will be ignored, except for the erase resume command. writing the erase resume command resumes the sector erase operation. the ad- dresses are ?on? cares when writing the erase sus- pend or erase resume command. when the erase suspend command is written during a sector erase operation, the chip will take between 0.1 m s and 20 m s to actually suspend the operation and go into erase suspended read mode (pseudo-read mode), at which time the user can read or program from a sec- tor that is not erase suspended. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq2 to toggle. polling dq2 on successive reads from a given sector provides the system the ability to determine if a sector is in erase suspend. after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for byte program. this program mode is known as the erase suspend-program mode. again, programming in this mode is the same as programming in the regular byte program mode, except that the data must be programmed to sectors that are not erase sus- pended. successively reading from the erase sus- pended sector while the device is in the erase suspend-program mode will cause dq2 to toggle. completion of the erase suspend operation can be de- termined two ways: n checking the status of the toggle bit dq2 n checking the status of the ry/by pin to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. however, another erase suspend command can be written after the device has resumed sector erase op- erations. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. an- other erase suspend command can be written after the chip has resumed erasing. write operation status address sensitivity of write status flags detailed in table 6 are all the status ?gs that can be used to check the status of the device for current mode operation. during sector erase, the part provides the status ?gs automatically to the i/o ports. the informa- tion on dq2 is address sensitive. this means that if an address from an erasing sector is consecutively read, then the dq2 bit will toggle. however, dq2 will not tog- gle if an address from a non-erasing sector is consec- utively read. this allows the user to determine which sectors are erasing and which are not. once erase suspend is entered, address sensitivity still applies. if the address of a non-erasing sector (that is, one available for read) is provided, then stored data can be read from the device. if the address of an eras- ing sector (that is, one unavailable for read) is applied, the device will output its status bits. con?mation of sta- tus bits can be done by doing consecutive reads to tog- gle dq2, which is active throughout the embedded erase mode, including erase suspend. in order to effectively use d a t a polling to determine if the device has entered into erase-suspended mode, it is necessary to apply a sector address from a sector being erased.
16 AM29LV008T/am29lv008b preliminary table 6. hardware sequence flags notes: 1. dq2 can be toggled when the sector address applied is that of an erasing or erase suspended sector. conversely, dq2 cannot be toggled when the sector address applied is that of a non-erasing or non-erase suspended sector. dq2 is therefore used to determine which sectors are erasing or erase suspended and which are not. 2. these status ?gs apply when outputs are read from the address of a non-erase-suspended sector. 3. if dq5 is high (exceeded timing limits), successive reads from a problem sector will cause dq2 to toggle. dq7: data polling the am29lv008 features d a t a polling as a method to indicate to the host system that the embedded algo- rithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the compliment of the data last written to dq7. upon completion of the em- bedded program algorithm, an attempt to read the de- vice will produce the true data last written to dq7. note that just at the instant when dq7 switches to true data, the other bits, dq6?q0, may not yet be true data. however, they will all be true data on the next read from the device. please note that data polling (dq7) may give an inaccurate result when an attempt is made to write to a protected sector. during an embedded erase algorithm, an attempt to read the device will pro- duce a ? at the dq7 output. upon completion of the embedded erase algorithm, an attempt to read the device will produce a ? at dq7. for chip erase, the d a t a polling is valid (dq7 = 1) after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the d a t a polling is valid after the last rising edge of the sector erase we pulse. d a t a polling must be performed at sector ad- dresses within any of the sectors being erased and not a sector that is within a protected sector. otherwise, the status may not be valid. just prior to the completion of embedded algorithm op- erations, dq7 may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq7 at one in- stant of time and in the next instance of time, that byte has valid data. depending on when the system sam- ples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq7 has valid data, dq0 dq6 may still provide write operation status. the valid data on dq0?q7 can be read on the next successive read attempt. the d a t a polling feature is only active during the em- bedded programming algorithm, embedded erase al- gorithm, erase suspend, erase suspend-program mode, or sector erase time-out (see table 6). if the user attempts to write to a protected sector, d a t a polling will be activated for about 1 m s; the device will then return to read mode, with data from the protected sector unchanged. if the user attempts to erase a pro- tected sector, toggle bit will be activated for about 50 m s; the device will then return to read mode, without having erased the protected sector. see figure 6 for the d a t a polling timing speci?ations and diagrams. dq6: toggle bit the am29lv008 also features a ?oggle bit as a method to indicate to the host system whether the em- bedded algorithms are in progress or completed. during an embedded program or erase algorithm, successive attempts to read data from the device will result in dq6 toggling between one and zero. once the status dq7 dq6 dq5 dq3 dq2 ry/by in progress programming dq7 toggle 0 0 no toggle 0 program/erase in auto-erase 0 toggle 0 1 (note 1) 0 erase suspend mode erase sector address 1 no toggle 0 0 toggle (note 1) 1 non-erase sector address data data data data data (note 2) 1 program in erase suspend dq7 (note 2) toggle 0 0 1 (note 2) 0 exceeded time limits programming dq7 toggle 1 0 no toggle 0 program/erase in auto-erase 0 toggle 1 1 (note 3) 0 program in erase suspend dq7 toggle 1 0 no toggle 0
AM29LV008T/am29lv008b 17 preliminary 3.0 v-only flash embedded program or erase algorithm is completed, dq6 will stop toggling and valid data can be read on the next successive attempts. during programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four-write-pulse sequence. during chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six-write-pulse sequence. during sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is active during the sector erase time-out. either ce or oe toggling will cause dq6 to toggle. if the user attempts to write to a protected sector, d a t a polling will be activated for about 1 m s; the device will then return to read mode, with data from the protected sector unchanged. if the user attempts to erase a pro- tected sector, toggle bit will be activated for about 50 m s; the device will then return to read mode, without having erased the protected sector. dq5: exceeded timing limits dq5 will indicate if the program or erase time has ex- ceeded the specied limits (internal pulse count). under these conditions, dq5 will produce a ? indicat- ing that the program or erase cycle was not success- fully completed. write operation status and reset command are the only operating functions under this condition. the device will draw active power under this condition. the dq5 failure condition will also appear if the user at- tempts to write a data ? to a bit that has already been programmed to a data ?? in this case, the dq5 failure condition is not guaranteed to happen, since the device was incorrectly used. please note that programming a data ? to a data ? should never be attempted, and only erasure should be used for this purpose. if pro- gramming to a data ? is attempted, the device should be reset. if the dq5 failure condition is observed while in sector erase mode (that is, exceeded timing limits), then dq2 can be used to determine which sector had the prob- lem. this is especially useful when multiple sectors have been loaded for erase. dq3: sector erase timer after the completion of the initial sector erase com- mand sequence, the sector erase time-out will begin. dq3 will remain low until the time-out is complete. d a t a polling (dq7) and toggle bit (dq6) are also valid after the ?st sector erase command sequence. if d a t a polling or the toggle bit indicates the device has been written with a valid sector erase command, dq3 may be used to determine if the sector erase timer window is still open. if dq3 is high (??, the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by the d a t a polling or toggle bit. if dq3 is low (??, the device will accept additional sector erase commands. to be certain the command has been accepted, the software should check the status of dq3 following each sector erase command. if dq3 was high on the sec- ond status check, the command may not have been ac- cepted. it is recommended that the user guarantee the time be- tween sector erase command writes be less than 80 m s by disabling the processor interrupts just for the dura- tion of the sector erase (30h) commands. this ap- proach will ensure that sequential sector erase command writes will be written to the device while the sector erase timer window is still open. dq2: toggle bit 2 this toggle bit, along with dq6, can be used to deter- mine whether the device is in the embedded erase al- gorithm or in erase suspend. successive reads from the erasing sector will cause dq2 to toggle during the embedded erase algorithm. if the device is in the erase-suspend-read mode, suc- cessive reads from the erase-suspended sector will cause dq2 to toggle. when the device is in the erase suspend-program mode, successive reads from the byte address of the non-erase suspended sector will in- dicate a logic ? at the dq2 bit. note that a sector which is selected for erase is not available for read in erase suspend mode. other sectors which are not selected for erase can be read in erase suspend. dq6 is different from dq2 in that dq6 toggles only when the standard program or erase, or erase suspend-program operation is in progress. if the dq5 failure condition is observed while in sector erase mode (that is, exceeded timing limits), the dq2 toggle bit can give extra information. in this case, the normal function of dq2 is modi?d. if dq5 is at logic ?? then dq2 will toggle with consecutive reads only at the sector address that caused the failure condition. dq2 will toggle at the sector address where the failure occurred and will not toggle at other sector addresses.
18 AM29LV008T/am29lv008b preliminary ry/by : ready/busy pin the am29lv008 provides a ry/by open-drain output pin as a way to indicate to the host system that the em- bedded algorithms are either in progress or have been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase com- mands with the exception of the erase suspend com- mand. if the am29lv008 is placed in an erase suspend mode, the ry/by output will be high. for pro- gramming, the ry/by is valid (ry/by =0) after the ris- ing edge of the fourth we pulse in the four write pulse sequence. for chip erase, the ry/by is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the ry/by is also valid after the rising edge of the sixth we pulse. since the ry/by pin is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resistor to v cc . table 7. toggle bit status notes: 1. these status ?gs apply when outputs are read from a sector that has been erase suspended. 2. these status ?gs apply when outputs are read from the addresses of the non-erase suspended sector. mode dq7 dq6 dq2 program dq7 toggles 1 erase 0 toggles toggles erase-suspend read (note 1) (erase-suspended sector) 1 1 toggles erase suspend program dq7 (note 2) toggles 1 (note 2) ce ry/by we last_bus_cycle t busy 20511c-4 figure 1. ry/by timing diagram
AM29LV008T/am29lv008b 19 preliminary 3.0 v-only flash reset : hardware reset pin the reset pin is an active low signal. a logic ? on this pin will force the device out of any mode that is cur- rently executing back to the reset state. this allows a system reset to take effect immediately without having to wait for the device to ?ish a long execution cycle. to avoid a potential bus contention during a system reset, the device is isolated from the data i/o bus by tri-stating the data output pins for the duration of the reset pulse. if reset is asserted during a program or erase oper- ation, the ry/by pin will remain low until the reset op- eration is internally complete. this will require between 1 m s and 20 m s. hence the ry/by pin can be used to signal that the reset operation is complete. otherwise, allow for the maximum reset time of 20 m s. if reset is asserted when a program or erase operation is not ex- ecuting (ry/by pin is high), the reset operation will be complete within 500 ns. asserting reset during a program or erase operation leaves erroneous data stored in the address locations being operated on at the time of device reset. these lo- cations need updating after the reset operation is com- plete. see figure 2 for timing speci?ations. the device enters i cc4 standby mode (200 na) when v ss 0.3 v is applied to the reset pin. the device can enter this mode at any time, regardless of the logical condition of the ce pin. furthermore, entering i cc4 during a program or erase operation leaves erroneous data in the address locations being operated on at the time of the reset pulse. these locations need updat- ing after the device resumes standard operations. after the reset pin goes high, a minimum latency period of 50 ns must occur before a valid read can take place. reset ry/by t rl t rrb 20511c-5 figure 2. device reset during a program or erase operation 0 v ry/by reset t rp 20511c-6 figure 3. device reset during read mode
20 AM29LV008T/am29lv008b preliminary data protection the am29lv008 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tions. during power-up, the device automatically resets the internal state machine to the read mode. also, with its control register architecture, alteration of the mem- ory contents only occurs after successful completion of the command sequences. the am29lv008 incorporates several features to pre- vent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (lock-out voltage). if v cc < v lko , the command register is disabled and all internal program/ erase circuits are disabled. under this condition, the device will reset to read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control levels are logically correct when v cc is above v lko (unless the reset pin is asserted). write pulse ?litch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not change the command registers. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be logical zero while oe is a logical one. power-up write inhibit power up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power up.
AM29LV008T/am29lv008b 21 preliminary 3.0 v-only flash embedded algorithms embedded program algorithm * device is either powered-down, erase inhibit, or program inhibit. start write program cmd sequence data poll device verify byte? no yes last address? no yes programming completed increment address 20511c-7 figure 4. embedded program algorithm bus operation command sequence comments standby* write program valid address/data read data polling to verify programming standby* compare data output to data expected
22 AM29LV008T/am29lv008b preliminary embedded erase algorithm start write erase cmd sequence data poll from device data = ffh? no yes erasure completed 20511c-8 figure 5. embedded erase algorithm bus operation command sequence comments standby write erase read d a t a polling to verify erasure standby compare output to ffh
AM29LV008T/am29lv008b 23 preliminary 3.0 v-only flash data polling algorithm start dq7 = data? yes no no dq5 = 1? no yes dq7 = data? yes fail pass 20511c-9 figure 6. data polling algorithm
24 AM29LV008T/am29lv008b preliminary toggle bit algorithm temporary sector unprotect algorithm start dq6 = toggle? no yes yes dq5 = 1? no yes dq6 = toggle? no fail pass 20511c-10 figure 7. toggle bit algorithm start perform erase or program operations reset = v ih temporary sector unprotect completed (note 2) reset = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. 20511c-11 figure 8. temporary sector unprotect algorithm
AM29LV008T/am29lv008b 25 preliminary 3.0 v-only flash absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . -65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . -55 c to +125 c voltage with respect to ground all pins except a9, oe and reset (note 1) . . . . . . . . . . . . . . . . . . . . -0.5 v to v cc +0.5 v v cc (note 1). . . . . . . . . . . . . . . . . . . . -0.5 v to +3.6 v a9 , oe , and reset (note 2). . . . . . -0.5 v to +13.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see tables 10 and 11. 2. minimum dc input voltage on pins a9, oe , and reset is -0.5 v. during voltage transitions, a9, oe , and reset may undershoot v ss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. see tables 10 and 11. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rat- ing conditions for extended periods may affect device re- liability. operating ranges commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0?c to +70?c industrial (i) devices ambient temperature (t a ). . . . . . . . . . ?0?c to +85?c extended (e) devices ambient temperature (t a ). . . . . . . . . ?5?c to +125?c v cc supply voltages v cc for AM29LV008T/b-90r. . . . . . . . +3.0 v to 3.6 v v cc for AM29LV008T/b-100, -120, -150 . . . . . . . . . . . . . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the func- tionality of the device is guaranteed.
26 AM29LV008T/am29lv008b preliminary dc characteristics cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 5 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when addresses remain stable for 200 ns. typical sleep mode current is 200 na. 4. not 100% tested. parameter symbol parameter description test conditions min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9 input load current v cc = v cc max ; a9 = 13.0 v 35 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active current (note 1) ce = v il, oe = v ih at 5 mhz 16 ma ce = v il, oe = v ih at 1 mhz 4 ma i cc2 v cc active current (notes 1, 2, and 4) ce = v il, oe = v ih 30 ma i cc3 v cc standby current v cc = v cc max ; ce , reset = v cc 0.3 v 5 m a i cc4 v cc standby current during reset v cc = v cc max ; ce = v cc 0.3 v; reset = v ss 0.3 v 5 m a i cc5 automatic sleep mode (note 3) v ih = v cc 0.3 v; v il = v ss 0.3 v 5 m a v il input low voltage -0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = -2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = -100 m a, v cc = v cc min v cc -0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v
AM29LV008T/am29lv008b 27 preliminary 3.0 v-only flash dc characteristics (continued) figure 8a. i cc current vs. time figure 8b. i cc vs. frequency note: addresses are switching at 1 mhz 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 20511c-11a supply current in ma time in ns note: t = 25 c 15 10 5 0 1 2345 3.6 v 2.7 v 20511c-11b frequency in mhz supply current in ma
28 AM29LV008T/am29lv008b preliminary ac characteristics read-only operations characteristics notes: 1. test conditions input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level: input: 1.5 v output: 1.5 v 2. output driver disable time 3. not 100% tested. parameter symbols speed option (note 1) jedec standard description test setup -90r -100 -120 -150 unit t avav t rc read cycle time (note 3) min 90 100 120 150 ns t avqv t acc address to output delay ce = v il oe = v il max 90 100 120 150 ns t elqv t ce chip enable to output delay oe = v il max 90 100 120 150 ns t glqv t oe output enable to output delay max 40 40 50 55 ns t ehqz t df chip enable to output high z (notes 2, 3) max 30 30 30 40 ns t ghqz t df output enable to output high z (notes 2, 3) max 30 30 30 40 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first (note 3) min0000ns t ready reset pin low to read mode (note 3) max 20 20 20 20 m s 2.7 k w in3064 or equivalent c l 6.2 k w 3.3 v in3064 or equivalent device under test in3064 or equivalent in3064 or equivalent notes: c l = 30 pf for 90 and 100 ns c l = 100 pf for 120 and 150 ns 20511c-12 figure 9. test conditions
AM29LV008T/am29lv008b 29 preliminary 3.0 v-only flash ac characteristics write (erase/program) operations notes: 1. the duration of the program or erase operation is variable and is calculated in the internal algorithms. 2. note 100% tested. parameter symbols description -90r -100 -120 -150 jedec standard unit t avav t wc write cycle time (note 2) min 90 100 120 150 ns t avwl t as address setup time min 0000ns t wlax t ah address hold time min 50 50 50 65 ns t dvwh t ds data setup time min 50 50 50 65 ns t whdx t dh data hold time min 0000ns t oes output enable setup time (note 2) min 0000ns t oeh output enable hold time read (note 2) min 0000ns toggle and data polling (note 2) min 10 10 10 10 ns t ghwl t ghwl read recovery time before write (oe high to we low) min0000ns t elwl t cs ce setup time min 0000ns t wheh t ch ce hold time min 0000ns t wlwh t wp write pulse width min 50 50 50 65 ns t whwl t wph write pulse width high min 30 30 30 35 ns t whwh1 t whwh1 programming operation typ 9999 m s t whwh2 t whwh2 sector erase operation (note 1) typ 1111sec t vcs v cc setup time min 50 50 50 50 m s t rb write recovery time from ry/by min0000ns t rh reset high time before read min 50 50 50 50 ns t rpd reset to power down time min 20 20 20 20 m s t busy program/erase valid to ry/by delay min 90 90 90 90 ns t vidr rise time to v id min 500 500 500 500 ns t rp reset pulse width min 500 500 500 500 ns t rrb reset low to ry/by high max 20 20 20 20 m s t rsp reset setup time for temporary sector unprotect min4444 m s
30 AM29LV008T/am29lv008b preliminary key to switching waveforms must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal 20 ns 20 ns +0.8 v ?.5 v 20 ns ?.0 v 20511c-13 figure 10. maximum negative overshoot waveform 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v 20511c-14 figure 11. maximum positive overshoot waveform
AM29LV008T/am29lv008b 31 preliminary 3.0 v-only flash switching waveforms t oh t ce t oe outputs we addresses ce oe high z output valid high z addresses stable t rc t acc t oeh t df 20511c-15 figure 12. ac waveforms for read operations t ce t ghwl t oe t cs oe we ce v cc t oh t ds t df data t ah addresses t dh t wp pd dq7 d out t whwh1_or_2 t wc t as t rc t wph t vcs 555h pa pa data polling a0h notes: 1. dq7 is the output of the complement of the data written to the device. 2. d out is the output of the data written to the device. 3. pa is the address of the memory location to be programmed. 4. pd is the data to be programmed at the byte address. 5. illustration shows the last two cycles of a four-bus-cycle sequence.. 20511c-16 figure 13. ac waveforms for program operations
32 AM29LV008T/am29lv008b preliminary switching waveforms oe ce addresses v cc we data aah 80h 555h 555h aaah 555h sa 30h 55h 55h aaah aah 10h for chip erase t ghwl t cs t ds t ah t dh t wp t wc t as t wph 555h for chip erase note: 1. sa is the sector address for sector erase. 20511c-17 figure 14. ac waveforms for chip/sector erase operations we ce t ch t oe t df t oh t oeh oe high z t ce t whwh1_or_2 dq7 dq0-dq6=invalid data high z dq0-dq6 valid data dq0-dq6 dq7 dq7=valid data * * dq7 = valid data (the device has completed the embedded operation.) 20511c-18 figure 15. ac waveforms for data polling during embedded algorithm operations
AM29LV008T/am29lv008b 33 preliminary 3.0 v-only flash switching waveforms oe t oeh ce we dq6=toggle data (dq0-dq7) dq6=toggle dq6=stop toggling dq0-dq7 data valid * t oe t oes dq6 stops toggling (the device has completed the embedded operation.) 20511c-19 figure 16. ac waveforms for toggle bit during embedded algorithm operations dq7 = valid data (the device has completed the embedded operation.) 20511c-20 figure 17. ry/by timing diagram during program/erase operations ce we ry/by t busy entire programming or erase operations the rising edge of the last we signal reset t ready t rp 20511c-21 figure 18. reset timing diagram
34 AM29LV008T/am29lv008b preliminary switching waveforms 20511c-22 figure 19. temporary sector unprotect timing diagram 0 v or 3 v 12 v program or erase command sequence reset ce we 0 v or 3 v t vidr t rsp
AM29LV008T/am29lv008b 35 preliminary 3.0 v-only flash ac characteristics write (erase/program) operations alternate ce controlled writes notes: 1. not 100% tested. 2. the duration of the program or erase operation is variable and is calculated in the internal algorithms. 3. does not include the preprogramming time. parameter symbols -90r -100 -120 -150 jedec standard description unit t avav t wc write cycle time (note 1) min 90 100 120 150 ns t avel t as address setup time min 0000ns t elax t ah address hold time min 50 50 50 65 ns t dveh t ds data setup time min 50 50 50 65 ns t ehdx t dh data hold time min 0000ns t oes output enable setup time min 0000ns t oeh output enable hold time read (note 1) min 0000ns toggle and data polling (note 1) min 10 10 10 10 ns t ghel t ghel read recovery time before write (oe high to we low) min0000ns t wlel t ws we setup time min 0000ns t ehwh t wh we hold time min 0000ns t eleh t cp ce pulse width min 50 50 50 65 ns t ehel t cph ce pulse width high min 30 30 30 35 ns t whwh1 t whwh1 programming operation typ 9999 m s t whwh2 t whwh2 sector erase operation (note 3) typ 1111sec
36 AM29LV008T/am29lv008b preliminary switching waveforms t ghwl t ws oe ce we v cc t ds data t ah addresses t dh t cp pd dq7 d out t whwh1_or_2 t wc t as t cph t vcs 555h pa pa data polling a0h notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the complement of the data written to the device. 4. d out is the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 20511c-23 figure 20. alternate ce controlled write operation timings
AM29LV008T/am29lv008b 37 preliminary 3.0 v-only flash erase and programming performance notes: 1. the typical program and erase times are considerably less than the maximum times since most bytes program or erase signi?antly faster than the worst case byte. the device enters the failure mode (dq5=?? only after the maximum times given are exceeded. see the section on dq5 for further information. 2. except for erase and program endurance, the typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 3. under worst case conditions of 90?c, v cc = 2.7 v, 100,000 cycles. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle sequence for the program command. see table 5 for further information on command de?itions. latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop pin capacitance (notes 1?) notes: 1. sampled, not 100% tested. 2. test conditions t a = 25?c, f = 1.0 mhz. parameter typ (note 2) max (note 3) unit comments sector erase time 1 15 s excludes 00h programming prior to erasure (note 4) chip erase time 19 s byte programming time 9 300 m s excludes system level overhead (note 5) chip programming time 9 27 s erase/program endurance 1,000,000 cycles minimum 100,000 cycles guaranteed min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe , and reset ) -1.0 v 13.0 v input voltage with respect to v ss on all i/o pins -1.0 v v cc + 1.0 v v cc current -100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf
38 AM29LV008T/am29lv008b preliminary data sheet revision summary for am29lv008 distinctive characteristics: rearranged bullets. renamed ?.7 to 3.6 volt, ex- tended voltage range... to ?ingle power supply opera- tion. under ?ingle power supply operation and ?igh performance bullets, de?ed standard and extended voltage ranges and added 90 ns speed option. com- bined ?dvanced power management and ?ow cur- rent consumption bullets into new ?ltra low power consumption bullet. under that bullet, revised the typ- ical standby and automatic sleep mode current speci? cations from 1 m a to 200 na; revised read current specication from 10 ma to 2 ma/mhz. combined ?ector protection and ?lexible sector architecture bullets. under ?xible sector architecture bullet, added temporary sector unprotect feature description. com- bined embedded program and embedded erase bul- lets under new ?mbedded algorithms bullet; removed designations. clari?d descriptions of sector protec- tion, erase suspend/resume, hardware reset pin, ready/busy pin, and data polling and toggle bits. general description: added text on new speed option and voltage range to the second paragraph. product selector guide: added -90r voltage range and speed option. pin con?uration: added new voltage range for -90r to v cc speci?ation. ordering information, standard products: the -90r speed option is now listed in the example. revised ?peed option section to indicate both volt- age ranges. valid combinations: added -90r speed option and voltage range. automatic sleep mode: revised addresses stable time to 200 ns and current draw to 200 na. table 5, command de?itions: grouped address designators pa, pd, ra, rd, and sa under the legend heading. modi?d sa de?ition to ac- commodate the sector protect verify command. since unlock addresses only require address bits a0?10 to be valid, the number of hexadecimal digits in the unlock addresses were changed from four to three. the re- maining upper address bits are don? care. removed ? designation from hexadecimal values in table and replaced with new note 1. revised notes 5 and 6 to in- dicate when commands are valid; are now new notes 4 and 5. expanded autoselect section to show each function separately: manufacturer id, device id, and sector protect verify. added note 3 to explain sector protect codes. in note 8, changed a13 to a11, added ?nless otherwise noted? is now new note 6. reset : hardware reset pin: fourth paragraph: revised standby mode speci?ation to 200 na. operating ranges: v cc supply voltages: added 3.0 to 3.6 v voltage range and -90r speed option. dc characteristics: cmos compatible: changed i cc1 from 30 ma maxi- mum at 6 mhz to 16 ma maximum at 5 mhz and 4 ma maximum at 1 mhz. changed i cc2 from 35 ma to 30 ma maximum. in the v ol speci?ation, changed the i ol test condition from 5.8 to 4.0 ma. in note 1, changed 6 mhz to 5 mhz. in note 3, changed address stable time from 300 ns to 200 ns; changed typical au- tomatic sleep mode current from 1 m a to 200 na. figure 8a, i cc current vs. time, and figure 8b, i cc vs. frequency: figure 8a illustrates current draw during the automatic sleep mode after the addresses are stable. figure 8b shows how frequency affects the current draw curves for both voltage ranges. ac characteristics: read only operations characteristics: added -90r column. test conditions, figure 9: added 90 ns speed to c l note. ac characteristics: write/erase/program operations: added the -90r col- umn. figure 13, ac waveforms for program operations: changed 5555h to 555h in addresses waveform to match command de?itions (table 5). figure 14, ac waveforms for chip/sector erase operations: changed 5555h to 555h in addresses waveform to match command de?itions (table 5). figure 19, temporary sector unprotect diagram: corrected callouts on reset waveform to ? v or 3 v? ac characteristics: alternate ce controlled writes: added the -90r col- umn. changed t ah from 45 to 50 ns for -100, from 50 to 65 ns for -150. changed t ds from 50 to 65 ns for -150. changed t cp from 45 to 50 ns for -100, from 50 to 65 ns for -150. changed t cph from 20 to 30 ns for -100, - 120; from 20 to 35 ns for -150.
AM29LV008T/am29lv008b 39 preliminary 3.0 v-only flash figure 20, alternate ce controlled write operation timings: changed 5555h to 555h in addresses waveform to match command de?itions (table 5). erase and programming performance: added typical chip erase speci?ation. renamed erase/program cycles speci?ation to erase/program endurance. corrected to indicate 1,000,000 cycle en- durance is typical, not maximum, and that 100,000 cycle endurance is minimum, not typical. revised note 1 to include write endurance; moved note 1 references in table to table head. consolidated and moved note 1 and note 3 references in table to table head. combined note 2 and note 5 into new note 1, which applies to the entire table; revised to indicate that dq5=1 after any maximum time. comments for program and erase now straddle parameter rows. separated the two sentences in note 4 into new notes 4 and 5; added corresponding note references to comment section.

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